Semiconductor device including metal-2 dimensional material-semiconductor contact

ABSTRACT

A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation of U.S. application Ser. No. 17/001,925, filed Aug. 25, 2020, which is a continuation of U.S. application Ser. No. 16/152,576, filed Oct. 5, 2018, which is a divisional of U.S. application Ser. No. 15/010,807, filed on Jan. 29, 2016, which claims the benefit of Korean Patent Application No. 10-2015-0070567, filed on May 20, 2015, and Korean Patent Application No. 10-2015-0110233, filed on Aug. 4, 2015, in the Korean Intellectual Property Office, the entire contents of each of the above-referenced applications are hereby incorporated by reference.

BACKGROUND 1. Field

Example embodiments relate to a semiconductor device, and more particularly, to a semiconductor device including a two-dimensional material layer that has a two-dimensional crystal structure and is interposed between a metal and a semiconductor to reduce a contact resistivity therebetween.

2. Description of the Related Art

A semiconductor device includes a metal and a semiconductor that are in contact with each other in a particular part of the semiconductor device to externally exchange electric signals. The metal has a lower resistivity than the semiconductor and can be more easily wired to the external environment. In this case, however, a contact resistivity is generated due to a hetero-contact between the semiconductor and metal.

To reduce such contact resistivity, various methods to reduce a Schottky energy barrier between a semiconductor and a metal have been suggested. For example, a metal having a work function of about 4 eV is used for an n-type semiconductor and a metal having a work function of about 5 eV is used for a p-type semiconductor. However, because a phenomenon occurs when a work function of a metal is pinned on a surface of a semiconductor, there is a limit in reducing the Schottky energy barrier regardless of a type of the metal. As another method, a depletion width may be reduced by doping a surface of a semiconductor contacting a metal to have a relatively high concentration. However, although a doping concentration needs to be further increased as a demand for a semiconductor device having a smaller size has gradually increased, there is a limit in methods of increasing a doping concentration, maintaining a stable doping state, and reducing a depletion width according to an increase in the doping concentration.

SUMMARY

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented example embodiments.

According to example embodiments, a semiconductor device includes a semiconductor layer including a well region doped to a first conductivity type and a source region and a drain region doped to a second conductivity type electrically opposite the first conductivity type, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer, the two-dimensional material layer having a two-dimensional crystal structure, and including a first two-dimensional material layer on the source region and a second two-dimensional material layer on the drain region. The metal layer includes a source electrode on the first two-dimensional material layer and a drain electrode on the second two-dimensional material layer.

The two-dimensional material layer may be formed of a carbon-based 2D material including at least one of graphene and nano crystalline graphene (nc-G).

The two-dimensional material layer may be formed of a transition metal dichalcogenide including at least one of MoS₂, WS₂, TaS₂, HfS₂, ReS₂, TiS₂, NbS₂, SnS₂, MoSe₂, WSe₂, TaSe₂, HfSe₂, ReSe₂, TiSe₂, NbSe₂, SnSe₂, MoTe₂, WTe₂, TaTe₂, HfTe₂, ReTe₂, TiTe₂, NbTe₂, and SnTe₂.

The two-dimensional material layer may include at least one of TiO_(x), NbO_(x), MnO_(x), VaO_(x), MnO₃, TaO₃, WO₃, MoCl₂, CrCl₃, RuCl₃, BiI₃, PbCl₄, GeS, GaS, GeSe, GaSe, PtSe₂, In₂Se₃, GaTe, InS, InSe, InTe, hexagonal BN (h-BN), and phosphorene.

The two-dimensional material layer may have a doped structure obtained by one of replacing some elements of the two-dimensional crystal structure with other elements and combining other elements to the two-dimensional crystal structure.

The two-dimensional material layer may be one of a nanowire pattern, a nano-slit pattern, a nano-dot pattern and a nano-hole pattern.

A thickness of the two-dimensional material layer may be such that a contact resistivity between the semiconductor layer and the metal layer is equal to or less than 10-7 Ωcm².

The thickness of the two-dimensional material layer may be within a range of about 0.3 nm to about 5 nm.

The two-dimensional material layer may include multiple layers of a single-layer two-dimensional crystal structure having a thickness T1, and the total thickness TD of the two-dimensional material layer may be a sum of each of the thicknesses T1 of the single-layer two-dimensional crystal structures.

A surface of the semiconductor layer contacting the two-dimensional material layer may be surface-treated with monolayer atoms.

The metal layer may include a metal material and the semiconductor layer may include a semiconductor material, and the semiconductor layer, the mixture layer between the two-dimensional material layer and the metal layer, the mixture layer including the metal material and the semiconductor material.

The semiconductor device may further include a gate insulating film on the well region between the source region and the drain region, a gate electrode on the gate insulating film, and a spacer surrounding side walls of the gate insulating film and the gate electrode.

Each of the first two-dimensional material layer and the second two-dimensional material layer may contact a lower surface of the spacer.

Each of the first two-dimensional material layer and the second two-dimensional material layer may contact a side surface of the spacer.

A doping concentration of each of the source region and the drain region may be equal to or higher than 10¹⁹/cm³.

According to example embodiments, a semiconductor device includes a gate insulating film between a gate electrode and an undoped semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and metal layer, the two-dimensional material layer having a two-dimensional crystal structure including non-carbon based two-dimensional crystals.

The metal layer may include a source electrode on the gate insulating film and facing a first side surface of the semiconductor layer, and a drain electrode on the gate insulating film and facing a second side surface of the semiconductor layer, and the two-dimensional material layer may include a first two-dimensional material layer between the source electrode and the first side surface of the semiconductor layer and a second two-dimensional material layer between the drain electrode and the second side surface of the semiconductor layer.

The first two-dimensional material layer may be bent to extend from the first side surface of the semiconductor layer up to a first region of an upper surface of the semiconductor layer, and the second two-dimensional material layer may be bent to extend from the second side surface of the semiconductor layer up to a second region of the upper surface of the semiconductor layer.

According to example embodiments, a semiconductor device includes a gate insulating film between an undoped semiconductor layer and a gate electrode, a first two-dimensional material layer adjacent to a first side surface of the gate insulating film, the first two-dimensional material layer having a two-dimensional crystal structure including non-carbon based two-dimensional crystals, a second two-dimensional material layer adjacent to a second side surface of the gate insulating film opposite the first side surface, the second two-dimensional material layer having a two-dimensional crystal structure including non-carbon based two-dimensional crystals, a source electrode on the first two-dimensional material layer, and a drain electrode on the second two-dimensional material layer.

The source electrode and the drain electrode may be spaced apart from the gate insulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects will become apparent and more readily appreciated from the following description of the example embodiments, taken in conjunction with the accompanying drawings in which:

FIG. 1 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to example embodiments;

FIG. 2 schematically illustrates an energy band diagram of a semiconductor device according to a comparative example, the semiconductor device not including a two-dimensional material layer;

FIG. 3A schematically illustrates an energy band diagram of the semiconductor device illustrated in FIG. 1 when a two-dimensional material layer therein is a non-carbon based two-dimensional crystal;

FIG. 3B schematically illustrates an energy band diagram of the semiconductor device illustrated in FIG. 1 when the two-dimensional material layer therein is a carbon-based two-dimensional crystal;

FIG. 4 is a graph showing a change in a contact resistivity according to a type of a two-dimensional material layer;

FIGS. 5 and 6 are cross-sectional views schematically illustrating structures of semiconductor devices having different numbers of two-dimensional material layers;

FIGS. 7A to 7D are plan views schematically illustrating examples of various patterns of a two-dimensional material layer;

FIG. 8 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to example embodiments;

FIG. 9 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to example embodiments;

FIG. 10 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to example embodiments; and

FIG. 11 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to example embodiments.

DETAILED DESCRIPTION

Reference will now be made in detail to a semiconductor device including contact of metal-two dimensional material-semiconductor, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Also, the size of each layer illustrated in the drawings may be exaggerated for convenience of explanation and clarity. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. In a layer structure, when a constituent element is disposed “above” or “on” to another constituent element, the constituent element may be only directly on the other constituent element or above the other constituent elements in a non-contact manner.

It will be understood that when an element is referred to as being “on,” “connected to,” “electrically connected to,” or “coupled to” to another component, it may be directly on, connected to, electrically connected to, or coupled to the other component or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to,” “directly electrically connected to,” or “directly coupled to” another component, there are no intervening components present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or section from another element, component, region, layer, and/or section. For example, a first element, component, region, layer, and/or section could be termed a second element, component, region, layer, and/or section without departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe the relationship of one component and/or feature to another component and/or feature, or other component(s) and/or feature(s), as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments may be described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature, their shapes are not intended to illustrate the actual shape of a region of a device, and their shapes are not intended to limit the scope of the example embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 is a cross-sectional view schematically illustrating a structure of a semiconductor device 100 according to example embodiments. Referring to FIG. 1, the semiconductor device 100 according to example embodiments may include semiconductor layers 101, 102, and 103, metal layers 106 and 107 electrically connected to the semiconductor layers 101, 102, and 103, and two-dimensional (2D) material layers 104 and 105 disposed between the semiconductor layers 101, 102, and 103 and the metal layers 106 and 107.

The semiconductor layers 101, 102, and 103 may include, for example, a well region 101 doped to a first conductivity type, a source region 102 doped to a second conductivity type opposite the first conductivity type, and a drain region 103 doped to the second conductivity type. Although FIG. 1 illustrates that the well region 101 is doped to a p-type conductivity and the source and drain regions 102 and 103 are doped to an n-type conductivity, this is a mere example and the well region 101 may be doped to an n-type conductivity and the source and drain regions 102 and 103 may be doped to a p-type conductivity. The well region 101 may be doped to a relatively low concentration of about 10¹⁴˜10 ¹⁸/cm³, and the source and drain regions 102 and 103 may be doped to a relatively high concentration of about 10¹⁹/cm³ or higher to reduce a depletion width.

The semiconductor layers 101, 102, and 103 may be a Group IV semiconductor, e.g., silicon (Si) or germanium (Ge), a Group III-V compound semiconductor, e.g., GaAs or GaP, a Group II-VI compound semiconductor, e.g., CdS or ZnTe, a Group IV-VI compound semiconductor, e.g., PbS, a Group IV-IV compound semiconductor, e.g., SiC, an oxide semiconductor, e.g., IGZO, or a 2D crystal structure semiconductor having a bandgap, e.g., MoS₂.

Also, upper surfaces of the source region 102 and the drain region 103 contacting the 2D material layers 104 and 105, which are described later, may be surface-treated with monolayer atoms to improve combination properties with the 2D material layers 104 and 105. Because the semiconductor, for example, silicon, generally has a relatively weak binding force with respect to a 2D material, the 2D material layers 104 and 105 respectively disposed on the source region 102 and the drain region 103 may be more easily detached from the source region 102 and the drain region 103. To prevent or inhibit the above phenomenon, the upper surfaces of the source region 102 and the drain region 103 may be surface-treated with elements exhibiting a desirable binding force with respect to the 2D material layers 104 and 105. For example, oxygen, sulfur, or selenium may be combined, in a monolayer, on the surfaces of the source region 102 and the drain region 103.

The 2D material layers 104 and 105 may include a first 2D material layer 104 disposed on the source region 102 and a second 2D material layer 105 disposed on the drain region 103. The 2D material layers 104 and 105 may be formed in a layered structure because the 2D material layers 104 and 105 are formed of a 2D material having a 2D crystal structure. Layers of the 2D material layers 104 and 105 may weakly interact with each other through the Van der Waals force. Accordingly, because the 2D material layers 104 and 105 may be formed in units of layers, a thickness thereof may be more easily adjusted.

The 2D material layers 104 and 105 may be formed of a carbon-based 2D material or a non-carbon based 2D material. The carbon-based 2D material may be formed in a crystal of a carbon element, for example, graphene or nano crystalline graphene (nc-G). General graphene is formed on catalyst metal in a chemical vapor deposition (CVD) method at a relatively high temperature process of about 700° C. to 1000° C. and a grain size thereof is about several micrometers. Because the general graphene may grow on metal, e.g., nickel (Ni) or copper (Cu), the general graphene may be transferred to another layer like semiconductor after growth. In contrast, nano crystalline graphene may be formed at a relatively low temperature of about 600° C. by an inductively coupled plasma CVD (ICP-CVD) method or a plasma enhanced CVD (PE-CVD) method, and a grain size thereof is about 100 nm or less. The nano crystalline graphene may grow on a semiconductor, for example, silicon, at a relatively low temperature.

The non-carbon based 2D material is a 2D material including elements other than carbon. A typical non-carbon based 2D material includes a transition metal dichalcogenide (TMD) that is a compound of transition metal and a chalcogen element. For example, TMD may include MoS₂, WS₂, TaS₂, HfS₂, ReS₂, TiS₂, NbS₂, SnS₂, MoSe₂, WSe₂, TaSe₂, HfSe₂, ReSe₂, TiSe₂, NbSe₂, SnSe₂, MoTe₂, WTe₂, TaTe₂, HfTe₂, ReTe₂, TiTe₂, NbTe₂, and SnTe₂.SnTe₂ There are various non-carbon based 2D materials other than TMD. For example, the non-carbon based 2D material may include hexagonal BN (h-BN), phosphorene, TiO_(x), NbO_(x), MnO_(x), VaO_(x), MnO₃, TaO₃, WO₃, MoCl₂, CrCl₃, RuCl₃, BiI₃, PbCl₄, GeS, GaS, GeSe, GaSe, PtSe₂, In₂Se₃, GaTe, InS, InSe, and InTe. The h-BN is formed in a hexagonal crystal structure by combining boron (B) and nitrogen (N). The phosphorene is a 2D allotropy of black phosphorus.

Although any of the above materials may be used for the 2D material layers 104 and 105, when the semiconductor layers 101, 102, and 103 are semiconductors having a 2D crystal structure, the material of the 2D material layers 104 and 105 may be chosen to be different from that of the semiconductor layers 101, 102, and 103.

Also, the 2D material layers 104 and 105 may use the above materials without modifying them, and/or the materials may be doped to further improve electrical characteristics of the semiconductor device 100. In other words, the 2D material layers 104 and 105 may have a doped structure by replacing some of elements forming the 2D crystal structure of the 2D material layers 104 and 105 with other elements or additionally combining other elements to the 2D crystal structure. For example, when the 2D material layers 104 and 105 are graphene, some of the carbon may be replaced with or combined with other elements, e.g., boron or nitrogen.

The metal layers 106 and 107 may include a source electrode 106 disposed on the first 2D material layer 104 and a drain electrode 107 disposed on the second 2D material layer 105. The metal layers 106 and 107 including the source electrode 106 and the drain electrode 107 may include, for example, a metal, e.g., magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chrome (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or an alloy thereof.

Also, the semiconductor device 100 may further include a gate insulating film 108 disposed on the well region 101 between the source region 102 and the drain region 103, a gate electrode 109 disposed on the gate insulating film 108, and a spacer 110 surrounding side walls of the gate insulating film 108 and the gate electrode 109. The spacer 110 may prevent or inhibit the gate insulating film 108 and the gate electrode 109 from directly contacting the source electrode 106 and the drain electrode 107. The gate insulating film 108 may be formed of SiO₂, SiN_(x), HfO₂, or Al₂O₃, and the gate electrode 109 may be formed of polysilicon or the same metal material as the metal layers 106 and 107. The spacer 110 may be formed of an insulation material, e.g., SiO₂ or SiN_(x).

As described above, the semiconductor device 100 according to example embodiments may include a 2D material interposed between semiconductor and metal. In detail, the semiconductor device 100 may include the first 2D material layer 104 interposed between the source region 102 and the source electrode 106 and the second 2D material layer 105 interposed between the drain region 103 and the drain electrode 107. Because a surface of the 2D material layers 104 and 105 have no reactant, a phenomenon in which work functions of metals of the source electrode 106 and the drain electrode 107 are pinned on the surfaces of the source region 102 and the drain region 103 may be prevented or inhibited. Accordingly, an effect according to a work function intrinsic to the metals of the source electrode 106 and the drain electrode 107 may occur, and as a result, contact resistivity may be reduced between the source region 102 and the source electrode 106, and between the drain region 103 and the drain electrode 107.

For example, FIG. 2 schematically illustrates an energy band diagram in a semiconductor device according to a comparative example having no 2D material layer 104 and 105. In FIG. 2, “Ec” denotes a level of a conduction band of semiconductor, “Ev” denotes a level of a valence band of semiconductor, and “W1” denotes a work function of metal. Referring to FIG. 2, in the case of a comparative example having no 2D material layers 104 and 105, because a work function of metal on an interface between semiconductor and metal is pinned to W1, a relatively high Schottky energy barrier is generated. Accordingly, the contact resistivity is increased on a contact surface of the semiconductor and the metal.

FIG. 3A schematically illustrates an energy band diagram in the semiconductor device 100 illustrated in FIG. 1 when the 2D material layers 104 and 105 are non-carbon based 2D crystals. In example embodiments, the 2D material layers 104 and 105 may cause an effect according to a work function W2 intrinsic to the metals of the source electrode 106 and the drain electrode 107. Accordingly, a Schottky energy barrier between the source region 102 and the source electrode 106 and between the drain region 103 and the drain electrode 107 may be lowered. Also, because the thicknesses of the 2D material layers 104 and 105 are sufficiently small such that tunneling may occur, electrons may tunnel through the 2D material layers 104 and 105. Accordingly, the contact resistivity between the source region 102 and the source electrode 106 and between the drain region 103 and the drain electrode 107 may be lowered. For example, the materials and thicknesses of the 2D material layers 104 and 105 may be selected such that the contact resistivity is equal to or less than 10⁻⁷ 0 cm².

FIG. 3B schematically illustrates an energy band diagram in the semiconductor device 100 illustrated in FIG. 1 when the 2D material layers 104 and 106 are carbon-based 2D crystals. As illustrated in FIG. 3B, a carbon-based 2D crystal, e.g., graphene, having no bandgap is different from the non-carbon based 2D crystal having a bandgap. When the carbon-based 2D crystal is used, the same effect as in the case of using the non-carbon based 2D crystal may be obtained.

FIG. 4 is a graph showing a change in contact resistivity according to types of the 2D material layers 104 and 105. In the graph of FIG. 4, titanium (Ti) is used as the metal and silicon (Si) is used as the semiconductor. Also, the leftmost of the graph of FIG. 4 indicates contact resistivity in a semiconductor device according to a comparative example having no 2D material layers 104 and 105, and graphene, h-BN, and MoS₂ are respectively used for “2D-1”, “2D-1”, “2D-2”, and “2D-3” sequentially in a direction toward the right, as the 2D material layers 104 and 105. As it may be seen from the graph of FIG. 4, the contact resistivity is highest when no 2D material layers 104 and 105 exist, whereas the contact resistivity may be reduced when the 2D material layers 104 and 105 are used.

Also, each of the 2D material layers 104 and 105 have a 2D layered crystal structure and may be formed layer by layer. Accordingly, the thicknesses of the 2D material layers 104 and 105 may be easily adjusted within 5 nm according to the number of layers of the 2D material layers 104 and 105 and uniformity of the thickness is improved. For example, FIGS. 5 and 6 are cross-sectional views schematically illustrating structures of the semiconductor devices 100 having different numbers of layers of the 2D material layers 104 and 105. Although FIG. 1 illustrates that each of the 2D material layers 104 and 105 is a single layer, each of the 2D material layers 104 and 105 may be formed in double layers as illustrated in FIG. 5, triple layers as illustrated in FIG. 6, or higher. Because the thickness of each of the 2D material layers 104 and 105 may be simply a multiple of the thickness of the single-layer 2D crystal structure, the thickness of each of the 2D material layers 104 and 105 may be simply determined by multiplication of the thickness of the single-layer 2D crystal structure and the number of layers thereof. For example, the number of layers may be selected such that the thickness of the 2D material layers 104 and 105 may be within a range of about 0.3 nm to 5 nm. As such, because the thickness uniformity of the 2D material layers 104 and 105 is desirable, uniform contact resistivity may be secured in an overall area between the source region 102 and the source electrode 106 and between the drain region 103 and the drain electrode 107.

Also, because the 2D material layers 104 and 105 generally have relatively high thermal stability, durability of the semiconductor device 100 may be improved. Also, because the 2D material layers 104 and 105 may function as a diffusion barrier with respect to semiconductor atoms and metal atoms, no additional diffusion barrier is needed to be formed between the source region 102 and the source electrode 106 and between the drain region 103 and the drain electrode 107. Accordingly, total resistivity of the semiconductor device 100 may be additionally reduced.

The 2D material layers 104 and 105 may completely fill the gap between the source region 102 and the source electrode 106 and between the drain region 103 and the drain electrode 107. However, when necessary, the 2D material layers 104 and 105 may be patterned such that a part of the source region 102 directly contacts the source electrode 106 and a part of the drain region 103 directly contacts the drain electrode 107. For example, FIGS. 7A to 7D are plan views schematically illustrating examples of various patterns of the 2D material layers 104 and 105. As illustrated in FIG. 7A, the 2D material layers 104 and 105 may be patterned in a form of a plurality of parallel nanowires. Also, as illustrated in FIG. 7B, the 2D material layers 104 and 105 may be patterned to have a form of a plurality of parallel nano-slits. As illustrated in FIG. 7C, the 2D material layers 104 and 105 may be patterned to have a form of a plurality of nano-dots disposed in a 2D array. In contrast, as illustrated in FIG. 7D, the 2D material layers 104 and 105 may be patterned to have a plurality of nano-holes disposed in a 2D array. As such, as the electrical characteristics, for example, a bandgap, of the 2D material layers 104 and 105 are changed by patterning the 2D material layers 104 and 105 in various forms, the characteristics of the semiconductor device 100 including the contact resistivity may be adjusted.

FIG. 8 is a cross-sectional view schematically illustrating a structure of a semiconductor device 200 according to example embodiments. In the case of the semiconductor device 100 illustrated in FIG. 1, the well region 101, the source region 102, and the drain region 103 may have the same surface height, and the 2D material layers 104 and 105 extend to contact a side surface of the spacer 110. In contrast, in the semiconductor device 200 of FIG. 8, the 2D material layers 104 and 105 extend to contact a lower surface of the spacer 110. To this end, an upper surface of the well region 101 may be formed to be higher than upper surfaces of the source region 102 and the drain region 103. For example, a difference in the height between the well region 101 and the source and drain regions 102 and 103 may be the same as the thicknesses of the 2D material layers 104 and 105. The 2D material layers 104 and 105 may extend to an interface between the spacer 110 and the gate insulating film 108 along a lower surface of the spacer 110. In example embodiments, the interface between the source and drain regions 102 and 103 and the well region 101 may match the interface between the spacer 110 and the gate insulating film 108. Accordingly, as a contact surface between the source and drain regions 102 and 103 and the 2D material layers 104 and 105 increases, the contact resistivity may be additionally decreased.

FIG. 9 is a cross-sectional view schematically illustrating a structure of a semiconductor device 300 according to example embodiments. When compared to the semiconductor device 100 of FIG. 1, the semiconductor device 300 of FIG. 9 may further include mixture layers 111 a and 111 b disposed between the 2D material layers 104 and 105 and the metal layers 106 and 107. In detail, the semiconductor device 300 may include a first mixture layer 111 a disposed between the first 2D material layer 104 and the source electrode 106, and a second mixture layer 111 b disposed between the second 2D material layer 105 and the drain electrode 107. The first mixture layer 111 a may be a mixture of a metal material forming the source electrode 106 and a semiconductor material forming the source region 102. Likewise, the second mixture layer 111 b may be a mixture of a metal material forming the drain electrode 107 and a semiconductor material forming the drain region 103. For example, when the semiconductor layers 101, 102, and 103 are formed of silicon, the mixture layers 111 a and 111 b may be formed of silicide. The mixture layers 111 a and 111 b may further lower the Schottky energy barrier so that the contact resistivity may be further reduced.

The above-described semiconductor devices 100, 200, and 300 are unipolar metal oxide semiconductor field effect transistors (MOSFET) in which the well region 101 in the semiconductor layers 101, 102, and 103 is doped to have a polarity opposite to the source and drain regions 102 and 103. However, the above-described principle may be applied not only to the unipolar MOSFET but also to any semiconductor device having hetero-contact between metal and semiconductor. For example, when all regions of a semiconductor layer are undoped or all regions of a semiconductor layer are doped to the same polarity, contact resistivity may be reduced by interposing a 2D material between semiconductor and metal.

For example, FIG. 10 is a cross-sectional view schematically illustrating a structure of a semiconductor device 400 according to example embodiments. Referring to FIG. 10, the semiconductor device 400 may include a gate electrode 201, a gate insulating film 202 disposed on the gate electrode 201, a semiconductor layer 203 disposed on the gate insulating film 202, metal layers 205 and 206 disposed on both sides of the semiconductor layer 203 and electrically contacting the semiconductor layer 203, and 2D material layers 204 a and 204 b disposed between the semiconductor layer 203 and the metal layers 205 and 206 and having a 2D crystal structure. The semiconductor layer 203 functions as a channel layer and may be undoped.

The metal layers 205 and 206 may include a source electrode 205 disposed on the gate insulating film 202 and facing one side of the semiconductor layer 203 and a drain electrode 206 disposed on the gate insulating film 202 and facing the other side of the semiconductor layer 203. Also, the gate electrode 201 may also be formed of a metal material. The above-described materials may be used as the metal material of the gate electrode 201, the source electrode 205, and the drain electrode 206.

The 2D material layers 204 a and 204 b may include a first 2D material layer 204 a disposed between the source electrode 205 and one side surface of the semiconductor layer 203 and a second 2D material layer 204 b disposed between the drain electrode 206 and the other side surface of the semiconductor layer 203. As illustrated in FIG. 10, the first 2D material layer 204 a may extend from one side surface of the semiconductor layer 203 to a partial area of the upper surface thereof. Also, the second 2D material layer 204 b may extend from the other side surface of the semiconductor layer 203 to another partial area of the upper surface thereof, not contacting the first 2D material layer 204 a. Accordingly, the 2D material layers 204 a and 204 b may be bent at about 90° C. between the side surface of the semiconductor layer 203 and the upper surface thereof. The 2D material layers 204 a and 204 b may be formed of the above-described 2D crystal material. In particular, a non-carbon based 2D crystal that is formed of crystals of elements other than carbon may be used for the 2D material layers 204 a and 204 b.

FIG. 11 is a cross-sectional view schematically illustrating a structure of a semiconductor device 500 according to example embodiments. While the semiconductor device 400 of FIG. 10 has a bottom gate structure in which the gate electrode 201 is disposed under the semiconductor layer 203, the semiconductor device 500 of FIG. 11 has top gate structure which is different from the bottom gate structure of the semiconductor device 400 of FIG. 10. Referring to FIG. 11, the semiconductor device 500 may include a substrate 221, an insulation layer 222 disposed on an upper surface of the substrate 221, a semiconductor layer 223 disposed on an upper surface of the insulation layer 222, a gate insulating film 225 disposed in a partial area of an upper surface of the semiconductor layer 223, a gate electrode 226 disposed on an upper surface of the gate insulating film 225, 2D material layers 224 a and 224 b disposed on another area of the upper surface of the semiconductor layer 223, and metal layers 227 and 228 respectively disposed on upper surfaces of the 2D material layers 224 a and 224 b. The semiconductor layer 223 functions as a channel layer and may be undoped.

The 2D material layers 224 a and 224 b may include a first 2D material layer 224 a and a second 2D material layer 224 b that are disposed adjacent to opposite side surfaces of the gate insulating film 225 on the upper surface of the semiconductor layer 223. For example, the gate insulating film 225 may be disposed in a central area of the upper surface of the semiconductor layer 223, and the first 2D material layer 224 a and the second 2D material layer 224 b may be disposed at the opposite sides of the gate insulating film 225. Although FIG. 11 illustrates that the first and second 2D material layers 224 a and 224 b are in closely contact with the gate insulating film 225, the first and second 2D material layers 224 a and 224 b may be spaced apart from the gate insulating film 225. In this case, a part of the upper surface of the semiconductor layer 223 may be exposed between the gate insulating film 225 and the first and second 2D material layers 224 a and 224 b.

Also, the metal layers 227 and 228 may include a source electrode 227 disposed on the first 2D material layer 224 a and a drain electrode 228 disposed on the second 2D material layer 224 b. The materials described with reference to FIG. 10 may be used for the metal layers 227 and 228 and the 2D material layers 224 a and 224 b. As illustrated in FIG. 11, the source electrode 227 and the drain electrode 228 may be partially and respectively disposed on the first 2D material layer 224 a and the second 2D material layer 224 b and may be spaced apart from the gate insulating film 225. Accordingly, parts of the upper surfaces of the first 2D material layer 224 a and the second 2D material layer 224 b may be exposed. Nevertheless, the source electrode 227 and the drain electrode 228 may completely cover the entire surfaces of the first 2D material layer 224 a and the second 2D material layer 224 b.

It should be understood that example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in other example embodiments.

While one or more example embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims. 

What is claimed is:
 1. A semiconductor device comprising: a semiconductor layer including a well region doped to a first conductivity type, and a source region and a drain region doped to a second conductivity type electrically opposite the first conductivity type; a source electrode electrically connected to the source region; a drain electrode electrically connected to the drain region; a first two-dimensional material layer between the source region and the source electrode; and a second two-dimensional material layer between the drain region and the drain electrode, wherein the first two-dimensional material layer and the second two-dimensional material layer comprise a nano crystalline graphene (nc-G), a grain size of the nano crystalline graphene being about 100 nm or less, wherein the first two-dimensional material layer and the second two-dimensional material layer comprise multiple layers or a single-layer of a two-dimensional crystal structure, and wherein a thickness of the first two-dimensional material layer or the second two-dimensional material layer is within a range of about 0.3 nm to about 5 nm.
 2. The semiconductor device of claim 1, wherein an element exhibiting a desirable binding force with respect to the first two-dimensional material layer and the second two-dimensional material layer is combined in a layer on an upper surface of the semiconductor layer
 3. The semiconductor device of claim 2, wherein the element includes at least one of oxygen element, sulfur element, and selenium element.
 4. The semiconductor device of claim 1, wherein the first two-dimensional material layer and the second two-dimensional material layer are patterned in one of a plurality of nanowires, a plurality of nano-slits, and a plurality of nano-dots.
 5. The semiconductor device of claim 4, wherein a part of the source region directly contacts the source electrode.
 6. The semiconductor device of claim 4, wherein a part of the drain region directly contacts the drain electrode.
 7. The semiconductor device of claim 1, further comprising: a gate insulating film on an upper surface of the well region; and a gate electrode on the gate insulating film, wherein the first two-dimensional material layer is adjacent to a first side surface of the gate insulating film and the second two-dimensional material layer is adjacent to a second side surface of the gate insulating film opposite the first side surface.
 8. The semiconductor device of claim 7, wherein the first two-dimensional material layer and the second two-dimensional material layer are detached to each other.
 9. The semiconductor device of claim 1, the source electrode is disposed on the first two-dimensional material layer and the drain electrode is disposed on the second two-dimensional material layer. 